1. Technical Field
The present invention generally relates to an improved data processing system and in particular to improved memory management in a data processing system. Still more particularly, the present invention relates to an improved intervention protocol for cache memory management in a data processing system.
2. Description of the Related Art
Multiprocessor systems having multilevel storage hierarchies often support an xe2x80x9cinterventionxe2x80x9d, a bus transaction in which a snooper responds to a request for data and sources the data rather than allowing the data to be sourced from the storage device to which the request was addressed. For example, if one level two (L2) cache snoops a read operation initiated by another L2 cache on the system bus directed at system memory, the first L2 cache may intervene in the read operation through a snoop response. The data is then sourced from the snooping cache to the requesting cache.
In a typical intervention scenario, a cache issues a read request on the system bus. Normally, the requested data would be sourced from main memory. With intervention, another cache containing the data may respond and source the data instead of the system memory. Upon seeing this response, the memory controller knows not to source the data, which is instead sourced directly by the intervening cache to the requesting cache via the system bus.
The most commonly supported intervention type is a modified intervention, where xe2x80x9cmodifiedxe2x80x9d refers to a coherency state within the modified/exclusive/shared/invalid (MESI) coherency protocol. If the first L2 cache described above snoops the read operation and determines that it contains the target cache line in a modified coherency state, the cache will intervene in the snooped operation to satisfy the request and to update the image of the data in system memory, maintaining memory coherency.
Some systems also support a shared intervention, in which the snooping L2 cache has the requested data in a shared coherency state but intervenes and satisfies the request. Typically shared intervention is supported where access latency to system memory is much longer (in processor or bus cycles) than the time required for request/response transactions on the system bus.
An intervention usually returns a full cache line (which may be, for example, 64 bytes) of data. Assuming the system data bus is eight bytes wide, eight bus cycles (or eight xe2x80x9cbeatsxe2x80x9d) are required to transfer the cache line. However, the requesting cache may only require a portion of the cache line, not the entire cache line, and may indicate this through an intra-cache line address portion of the address driven for the request. Thus, the bus cycles consumed in transferring the portions of the cache line which are not required by the requesting cache are effectively wasted if the remaining portion of the cache line data is unlikely to be required in the near future (before invalidation of the cache line within the requesting cache).
In some situations, an intervening cache may desire to have the requesting cache skip caching of the target data. For example, the intervening cache may predict that it will be modifying the data again shortly, and wish to avoid having to transmit a request to invalidate copies of the data within other caches (i.e., maintaining the cache line in an exclusive state after the intervention).
It would be desirable, therefore, to provide a system improving the xe2x80x9cintelligencexe2x80x9d of cache management, and in particular to reducing bus bandwidth consumed by interventions and subsequent related operations.
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide improved memory management in a data processing system.
It is yet another object of the present invention to provide to an improved intervention protocol for cache memory management in a data processing system.
The foregoing objects are achieved as is now described. Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather than the entire cache line. For example, if the intervening cache determines that the requesting cache would likely be required to invalidate the cache line soon after receipt, less than the full cache line may be sourced to the requesting cache. The requesting cache will not cache less than a full cache line, but may forward the received data to the processor supported by the requesting cache. Data bus bandwidth utilization may therefore be reduced. Additionally, the need to subsequently invalidate the cache line within the requesting cache is avoided, together with the possibility that the requesting cache will retry an operation requiring invalidation of the cache line.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.